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SN54/74LS259 8-BIT ADDRESSABLE LATCH
The SN54 / 74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW common Clear for resetting all latches, as well as, an active LOW Enable.
8-BIT ADDRESSABLE LATCH
LOW POWER SCHOTTKY
* * * * * *
Serial-to-Parallel Conversion Eight Bits of Storage With Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear CONNECTION DIAGRAM DIP (TOP VIEW)
16
J SUFFIX CERAMIC CASE 620-09
1
VCC 16
C 15
E 14
D 13
Q7 12
Q6 11
Q5 10
Q4 9
16 1
N SUFFIX PLASTIC CASE 648-08
1 Ao PIN NAMES
2 A1
3 A2
4 Q0
5 Q1
6 Q2
8 7 Q3 GND LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 5 (2.5) U.L.
16 1
D SUFFIX SOIC CASE 751B-03
A0, A1, A2 D E C Q0 to Q7
Address lnputs Data Input Enable (Active LOW) Input Clear (Active LOW) input Parallel Latch Outputs (Note b)
0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 10 U.L.
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA
FAST AND LS TTL DATA 5-1
SN54/74LS259
LOGIC DIAGRAM
E
14
D
13 1
A0
2
A1
A2
3 15
C
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS
4
5
6
7
9
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FUNCTIONAL DESCRIPTION The SN54 / 74LS259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the MODE SELECTION
E L H L H C H H L L MODE Addressable Latch Memory Active HIGH Eight-Channel Demultiplexer Clear C E D A0 LHX X LLL L LLH L LLL H LLH H *** *** *** *** *** LLH H HHX H H H H * * * * * H H I L L L * * * * * L L I H L H * * * * * L H X L L H H A1 X L L L L * * * * * H X L L L L * * * * * H H A2 X L L L L Q0 L L H L L
addressed output will follow the state of the D input with all other inputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the SN54 / 74LS259 as an addressable latch, changing more then one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The truth table below summarizes the operations. TRUTH TABLE PRESENT OUTPUT STATES
Q1 L L L L H Q2 L L L L L Q3 L L L L L * * * * * L Q4 L L L L L Q5 L L L L L Q6 L L L L L Q7 L L L L L MODE Clear Demultiplex
H X L L L L
L QN-1 L H QN-1 QN-1
L
L
L
L
L
H Memory
QN-1 QN-1 L H
QN-1 QN-1 QN-1 QN-1
QN-1
Addressable Latch
X = Don't Care Condition L = LOW Voltage Level H = HIGH Voltage Level QN-1 = Previous Output State
* * * * * QN-1 QN-1 L H
H H
H H
QN-1 QN-1
FAST AND LS TTL DATA 5-2
SN54/74LS259
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current -20 - 0.4 - 100 36 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter P Turn-Off Delay, Enable to Output Turn-On Delay, Enable to Output Turn-Off Delay, Data to Output Turn-On Delay, Data to Output Turn-Off Delay, Address to Output Turn-On Delay, Address to Output Turn-On Delay, Clear to Output Min Typ 22 15 20 13 24 18 17 Max 35 24 32 21 38 29 27 Unit Ui ns ns ns ns ns ns ns Test C di i T Conditions
CL = 15 pF pF
AC SET-UP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol S bl ts tW th th Input Setup Time Pulse Width, Clear or Enable Hold Time, Data Hold Time, Address Parameter P Min 20 15 5.0 20 Typ Max Unit Ui ns ns ns ns
FAST AND LS TTL DATA 5-3
SN54/74LS259
AC WAVEFORMS
D D tw E tPHL Q OTHER CONDITIONS: C = H, A = STABLE tPLH 1.3 V OTHER CONDITIONS: E = L, C = H, A = STABLE tw 1.3 V Q 1.3 V tPHL 1.3 V 1.3 V tPLH 1.3 V
Figure 2. Turn-on and Turn-off Delays, Data to Output
Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width
A1
1.3 V
1.3 V
D ts(H) th(H) ts(L) th(L) 1.3 V
A1 Q1
1.3 V tPHL 1.3 V
1.3 V tPLH 1.3 V
E
Q
Q=D
Q=D
OTHER CONDITIONS: E = L, C = L, D = H
OTHER CONDITIONS: C = H, A = STABLE
Figure 3. Turn-on and Turn-off Delays, Address to Output
Figure 4. Setup and Hold Time, Data to Enable
C
1.3 V tPHL 1.3 V
A ts E
STABLE ADDRESS
Q OTHER CONDITIONS: E = H
Figure 5. Turn-on Delay, Clear to Output
OTHER CONDITIONS: C = H
Figure 6. Setup Time, Address to Enable (See Notes 1 and 2)
NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
FAST AND LS TTL DATA 5-4

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